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TDA7342
DIGITALLY CONTROLLED AUDIO PROCESSOR
PRODUCT PREVIEW
INPUT MULTIPLEXER - TWO STEREO AND ONE MONO INPUTS - ONE QUASI DIFFERENTIAL INPUT - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES FULLY PROGRAMMABLE LOUDNESS FUNCTION VOLUME CONTROL IN 0.3dB STEPS INCLUDING GAIN UP TO 20dB ZERO CROSSING MUTE, SOFT MUTE AND DIRECT MUTE BASS AND TREBLE CONTROL FOUR SPEAKER ATTENUATORS - FOUR INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCE AND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS DESCRIPTION The audioprocessor TDA7342 is an upgrade of the TDA731X audioprocessor family. Due to a highly linear signal processing, using CMOS-switching techniques instead of standard
TQFP 32
ORDERING NUMBER: TDA7342
bipolar multipliers, very low distortion and very low noise are obtained. Several new features like softmute, and zero-crossing mute are implemented. The soft Mute function can be activated in two ways: 1 Via serial bus (Mute byte, bit D0) 2 Directly on pin 21 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology.
October 1995
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
OUT(L) 16 21 SPKR ATT 25 MUTE ZERO CROSS + MUTE LOUD+ VOL BASS SPKR ATT 23 MUTE 28 SOFT MUTE SERIAL BUS DECODER + LATCHES 27 26 SPKR ATT R3 24 M R2 R1 ZERO CROSS + MUTE LOUD+ VOL MUTE TREBLE BASS TREBLE L3 15 9 32 18 17
IN(L)
LOUD(L) TREBLE(L)
SM BIN(L)
C1 L1 L2 M
L1
13
BOUT(L)
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C17 100nF C11 C13 47nF C18 100nF C19 2.7nF R2 4.7K OUT LEFT FRONT OUT LEFT REAR SCL SDA DIGGND BUS INPUT SELECTOR + GAIN OUT RIGHT FRONT SPKR ATT 22 MUTE 29 CREF 10F C9 C10 OUT(R) IN(R) 3 2 4 LOUD(R) C12 47nF 14 CSM CSM 47nF 20 19 BOUT(R) C14 100nF R1 4.7K 1 BIN(R) C15 100nF TREBLE(R)
D94AU104B
TDA7342
BLOCK DIAGRAM
LEFT INPUTS
L2
12
C2
C6
L3
11
CD
CD GND
10
C3
C7
R3
5
C8
MONO INPUT
M
8
R2
6
RIGHT INPUTS
C4
R1
7
C5
SUPPLY
OUT RIGHT REAR
30
31
VS
C16 2.7nF
TDA7342
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
PIN CONNECTION
DIG GND
32 31 30 29 28 27 26 25 TR R IN R OUT R LOUD R IN R3 IN R2 IN R1 MONO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IN L LOUD L CD GND OUT L IN L3 IN L2 IN L1 CSM 24 23 22 21 20 19 18 17 OUT RF OUT LR OUT RR SM BOUT R BIN R BOUT L BIN L
OUT LF
CREF
GND
TR L
SDA
SCL
VS
D94AU105A
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-pins Value 150 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Volume Control 0.3dB step Treble Control 2dB step Bass Control 2dB step Fader and Balance Control 1.25dB step Input Gain 3.75dB step Mute Attenuation -59.7 -14 -10 -38.75 0 100 Parameter Min. 6 2.1 Typ. 9 2.6 0.01 106 100 20 +14 +18 0 11.25 0.08 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB dB
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TDA7342
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT SELECTOR
RI VCL SI RL GI MIN GI MAX Gstep eN VDC Input Resistance Clipping Level Input Separation Output Load Resistance Minimum Input Gain Maximum Input Gain Step Resolution Input Noise DC Steps 20Hz to 20 KHz unweighted Adiacent Gain Steps GIIN to GIMAX d 0.3% 70 2.1 80 2 -0.75 10.25 2.75 0 11.25 3.75 2.3 1.5 3 10 0.75 12.25 4.75 100 2.6 100 130 K VRMS dB K dB dB dB V mV mV
DIFFERENTIAL INPUT ( IN 3)
RI CMRR d eIN GDIFF Input Resistance Common Mode Rejection Ratio Distortion Input Noise Differential Gain Input selector BIT D6 = 0 (0dB) Input selector BIT D6 = 1(-6dB) VCM = 1VRMS ; f = 10KHz VI = 1VRMS 20Hz to 20KHz; Flat; D6 = 0 D6 = 0 D6 = 1 -1 -7 f =1KHz 10 14 48 45 15 20 75 70 0.01 5 0 -6 1 -5 0.08 20 30 K K dB dB % V dB dB
VOLUME CONTROL
RI GMAX AMAX ASTEPC ASTEPF EA Et VDC Input Resistance Maximum Gain Maximum Attenuation Step Resolution Coarse Atten. Step Resolution Fine Attenuation Attenuation Set Error Tracking Error DC Steps Adiacent Attenuation Steps From 0dB to AMAX -3 0 0.5 G = 20 to -20dB G = -20 to -58dB 35 18.75 57.7 0.5 0.11 -1.25 -3 50 20 59.7 1.25 0.31 0 21.25 62.7 2.0 0.51 1.25 2 2 3 5 K dB dB dB dB dB dB dB mV mV
LOUDNESS CONTROL
RI AMAX Astep Internal Resistor Maximum Attenuation Step Resolution Loud = On 35 17.5 0.5 50 18.75 1.25 65 20.0 2.0 K dB dB
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TDA7342
ELECTRICAL CHARACTERISTICS (continued.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
ZERO CROSSING MUTE
VTH Zero Crossing Threshold (note 1) WIN = 11 WIN = 10 WIN = 01 WIN = 00 AMUTE VDC Mute Attenuation DC Step 0dB to Mute 80 20 40 80 160 100 0 3 mV mV mV mV dB mV
SOFT MUTE
AMUTE TDON TDOFF VTHSM RINT VSMH VSML Mute Attenuation ON Delay Time OFF Current Soft Mute Threshold Pullup Resistor (pin 21) (pin 21) Level High (pin 21) Level Low Soft Mute Active (note 2) CCSM = 22nF; 0 to -20dB; I = IMAX CCSM = 22nF; 0 to -20dB; I = IMIN VCSM = 0V; I = IMAX VCSM = 0V; I = IMIN 1.5 35 3.5 1 45 0.7 20 25 60 1 35 50 1 2.5 50 3.5 65 1.7 55 75 dB ms ms A A V K V V
BASS CONTROL
BBOOST BCUT Astep Rg Max Bass Boost Max Bass Cut Step Resolution Internal Feedback Resistance 15 -8.5 1 45 13 1 18 -10 2 65 14 2 20 -11.5 3 85 15 3 dB dB dB K
TREBLE CONTROL
C RANGE Astep Control Range Step Resolution dB dB
SPEAKER ATTENUATORS
C RANGE Astep AMUTE EA VDC Control Range Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Adjacent Attenuation Steps 0 Data Word = XXX11111 35 0.5 80 37.5 1.25 100 1.25 3 40 2.00 dB dB dB dB mV
AUDIO OUTPUT
Vclip RL RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level 3.5 d = 0.3% 2.1 2 30 3.8 100 4.1 2.6 Vrms K V
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TDA7342
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
GENERAL
VCC ICC PSRR e NO Et S/N SC d Supply Voltage Supply Current Power Supply Rejection Ratio Output Noise Total Tracking Error Signal to Noise Ratio Channel Separation Distortion VIN =1V f = 1KHz B = 20 to 20kHz "A" weighted Output Muted (B = 20 to 20kHz flat) All Gains 0dB (B = 20 to 20kHz flat) AV = 0 to -20dB AV = -20 to -60dB All Gains = 0dB; VO = 1Vrms 80 6 5 60 9 10 80 65 2.5 5 0 0 106 100 0.01 0.08 15 1 2 10.2 15 V mA dB dB V V dB dB dB dB %
BUS INPUTS
VIL V lN IlN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 1 V V A V
Note 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold Note 2: Internall pullup resistor to Vs/2; "LOW" = softmute active
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TDA7342
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7342 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. Byte Format Every byte transferred to the SDA line must conFigure 3: Data Validity on the I2CBUS tain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Figure 4: Timing Diagram of I2CBUS
2 Figure 5: Acknowledge on the I CBUS
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TDA7342
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte,(the LSB bit determines read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB S 1 0 0 0 1 0
LSB
MSB X X I
LSB A3 A2 A1 A0 ACK
MSB DATA
LSB
ACK P
0 R/W ACK X
ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used MAX CLOCK SPEED 500kbits/s AUTO INCREMENT If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled SUBADDRESS (receive mode)
MSB X X X I A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 LSB A0 0 1 0 1 0 1 0 1 0 Input Selector Loudness Volume Bass, Treble Speaker Attenuator LF Speaker Attenuator LR Speaker Attenuator RF Speaker Attenuator RR Mute FUNCTION
TRANSMITTED DATA Send Mode
MSB X X X X X SM ZM LSB X
ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chipaddress.
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TDA7342
DATA BYTE SPECIFICATION X = not relevant; set to "1" during testing Input Selector
MSB D7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D6 D5 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 IN 2 IN 1 AM mono not used not used not allowed not allowed 11.25dB gain 7.5dB gain 3.75dB gain 0dB gain 0dB differential input gain ( IN3 ) -6dB differential input gain ( IN3 ) FUNCTION IN 3 (differential input)
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1 Loudness
MSB D7 X X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X X D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 FUNCTION 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB -10dB -11.25dB -12.5dB -13.75dB -15dB -16.25dB -17.5dB -18.75dB Loudness OFF (1)
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
NOTE 1: If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency response. D0 to D3 determine the attenuation level.
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TDA7342
Mute
MSB D7 D6 D5 D4 D3 D2 D1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 0 1 0 LSB D0 1 1 1 Soft Mute On Soft Mute with fast slope (I = IMAX) Soft Mute with slow slope (I = IMIN) Direct Mute Zero Crossing Mute On Zero Crossing Mute Off (delayed until next zero crossing) Zero Crossing Mute and Pause Detector Reset 160mV ZC Window Threshold (WIN = 00) 80mV ZC Window Threshold (WIN = 01) 40mV ZC Window Threshold (WIN = 10) 20mV ZC Window Threshold (WIN = 11) Nonsymmetrical Bass Cut (note 4) Symmetrical Bass Cut FUNCTION
An additional direct mute function is included in the Speaker Attenuators.
Note 4: Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
Speaker Attenuators
MSB D7 X X X X X X X X X X X X X D6 X X X X X X X X X X X X X D5 X X X X X X X X X X X X X 0 0 1 1 1 0 1 0 1 1 1 1 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER ATTENUATOR LF, LR, RF, RR 1.25dB step 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB step 0dB -10dB -20dB -30dB Speaker Mute
For example an attenuationof 25dB on a selected output is given by: X X X1 0 1 0 0
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TDA7342
Bass Treble
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 FUNCTION TREBLE STEP -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB BASS STEPS -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 146B 18dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
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TDA7342
Volume
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LSB D0 0 1 0 1 FUNCTION 0.31dB Fine Attenuation Steps 0dB -0.31dB -0.62dB -0.94dB 1.25dB Coarse Attenuation Steps 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB Gain / Attenuation Steps 20dB 10dB 0dB -10dB -20dB -30dB -40dB -50dB
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1 Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
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TDA7342
TQFP32 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 0(min.), 7(max.) 0.75 0.018 1.40 0.37 mm TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 0.030 0.055 0.015 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008
D D1 D3 A1
17 16
0.10 mm .004 Seating Plane
A A2
24 25
E3
E1
B
32 1 8
9
E
B C L K
e L1
TQFP32
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TDA7342
Purchase of I2C Components of SGS-THOMSON Microlectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1993 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A.
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